march 1998 f dt459n n -channel enhancement mode field effect transistor general description features absolute maximum ratings t a = 25 o c unless otherwise noted symbol parameter f dt459n units v dss drain-source voltage 30 v v gss gate-source voltage - continuous 20 v i d maximum drain current - continuous (note 1a) 6.5 a - pulsed 20 p d maximum power dissipation (note 1a ) 3 w (note 1 b) 1.3 (note 1c ) 1.1 t j ,t stg operating and storage temperature range -55 to 150 c thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1a) 42 c/w r q jc thermal resistance, junction-to-case (note 1) 12 c/w * order option j23z for cropped center drain lead. fdt459n rev.c 6.5 a , 3 0 v. r ds(on ) = 0.035 w @ v gs = 10 v r ds(on ) = 0.055 w @ v gs = 4.5 v. high density cell design for extremely low r ds(on) . high power and current handling capability in a widely used surface mount package. soic-16 supersot tm -3 supersot t m -8 so-8 sot-223 supersot t m -6 these n -c hannel enhancement mode power field effect transistors are produced using fairchild 's proprietary, high cell density, dmos technology. this very high density process is especially tailored to minimize on-state resistance, provide superior switching performance. these products are well suited to low voltage, low current applications such as notebook computer power management, battery powered circuits, and dc motor control. d d s g d s g ? 1998 fairchild semiconductor corporation
electrical characteristics (t a = 25 o c unless otherwise noted ) symbol parameter conditions min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a 30 v d bv dss / d t j breakdown voltage temp. coefficient i d = 250 a , referenced to 25 o c 33 mv/ o c i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v 1 a t j =5 5c 10 a i gssf gate - body leakage, forward v gs = 20 v, v ds = 0 v 100 na i gssr gate - body leakage, reverse v gs = - 20 v , v ds = 0 v -100 na on characteristics (note 2 ) v gs (th) gate threshold voltage v ds = v gs , i d = 250 a 1 1.6 2 v d v gs(th) / d t j gate threshold voltage temp.coefficient i d = 250 a , referenced to 25 o c -4.2 mv/ o c r ds(on) static drain-source on-resistance v gs = 10 v, i d = 6.5 a 0.031 0.035 w t j =12 5c 0.044 0.06 v gs = 4.5 v, i d = 5.5 a 0.046 0.055 i d(on) on-state drain current v gs = 10 v, v ds = 5 v 20 a g fs forward transconductance v ds = 10 v, i d = 6 .5 a 16 s dynamic characteristics c iss input capacitance v ds = 15 v, v gs = 0 v, f = 1.0 mhz 365 pf c oss output capacitance 210 pf c rss reverse transfer capacitance 70 pf switching ch aracteristics (note 2 ) t d(on ) turn - on delay time v dd = 15 v, i d = 1 a, v gs = 10 v, r gen = 6 w 5.2 11 ns t r turn - on rise time 8.2 16 ns t d(off) turn - off delay time 6 12 ns t f turn - off fall time 16 26 ns q g total gate charge v ds = 10 v, i d = 6 .5 a, v gs = 10 v 12 17 nc q gs gate-source charge 2.2 nc q gd gate-drain charge 3 nc drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current 2.5 a v sd drain-source diode forward voltage v gs = 0 v, i s = 2.5 a (note 2 ) 0.8 1.2 v notes: 1 . r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the s older mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. typical r q ja using the board layouts shown below on fr-4 pcb in a still air environment : scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300 s, duty cycle < 2.0% fdt459n rev.c a. 42 o c/w when mounted on a 1 in 2 pad of 2oz cu . b . 95 o c/w when mounted on a 0.066 in 2 pad of 2oz cu . c. 110 o c/w when mounted on a 0.00123 in 2 pad of 2oz cu .
fdt459n rev.c typical electrical characteristics figure 1. on-region characteristics . figure 2. on-resistance variation with drain current and gate voltage . figure 3. on-resistance variation with temperature . figure 5 . transfer characteristics. figure 4 . on-resistance variation with gate-t o -source voltage. -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 t , junction temperature (c) drain-source on-resistance j r normalized ds(on) v = 10v gs i = 6.5a d 0 1 2 3 4 5 0 5 10 15 20 25 30 v , drain-source voltage (v) i , drain-source current (a) v = 10v gs ds d 5.0 6.0 3.0 3.5 4.0 4.5 r , normalized ds(on) 0 5 10 15 20 25 30 0.5 1 1.5 2 2.5 3 3.5 i , drain current (a) drain-source on-resistance v = 3.5v gs d 5.0 4.0 10 4.5 6.0 2 4 6 8 10 0.02 0.04 0.06 0.08 0.1 0.12 0.14 v , gate to source voltage (v) gs r , on-resistance (ohm) ds(on) i = 6.5a d t = 125c j 25c 1 2 3 4 5 6 0 5 10 15 20 25 v , gate to source voltage (v) i , drain current (a) v = 10v ds gs d t = -55c j 125c 25c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0.0001 0.001 0.01 0.1 1 20 v , body diode forward voltage (v) i , reverse drain current (a) 25c -55c v = 0v gs sd s t = 125c j figure 6 . body diode forward voltage varia tion with source current and temperature.
fdt459n rev.c figure 10 . single pulse maximum power dissipation. figure 8. capacitance characteristics . figure 7 . gate charge characteristics. figure 9. maximum safe operating area. typical electrical characteristics 0 2 4 6 8 10 12 14 0 2 4 6 8 10 q , gate charge (nc) v , gate-source voltage (v) g gs v = 5v ds 10v i = 6.5a d 15v 0.1 0.2 0.5 1 2 5 10 20 30 50 0.01 0.05 0.1 0.5 1 2 5 10 20 40 v , drain-source voltage (v) i , drain current (a) rds(on) limit d a dc ds 1s 100ms 10ms 1ms 10s v =10v single pulse r = see note 1c t = 25c q ja gs a 100us 0.0001 0.001 0.01 0.1 1 10 100 300 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance r(t), normalized effective 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 duty cycle, d = t / t 1 2 r (t) = r(t) * r r = see note 1c t - t = p * r (t) a j p(pk) t 1 t 2 q ja q ja q ja q ja figure 11 . transient thermal response curve . note: thermal characterization performed using the conditions described in note 1c . transient thermal response will change depending on the circuit board design. 0.1 0.3 1 3 10 30 30 50 100 200 400 1000 v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0 v gs c oss c rss 0.001 0.01 0.1 1 10 100 300 0 40 80 120 160 200 single pulse time (sec) power (w) single pulse r = see note 1c t = 25c q ja a
disclaimer fairchild semiconductor reserves the right to make changes without further notice t o any products herein t o improve reliability , function or design. fairchild does not assume any liability arising out of the applica tion or use of any product or circuit described herein; neither does it convey any license under its p a tent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production optologic? optoplanar? pacman? pop? power247? powertrench qfet? qs? qt optoelectronics? quiet series? silent switcher fast fastr? frfet? globaloptoisolator? gto? hisec? isoplanar? littlefet? microfet? micropak? microwire? rev. h4 a acex? bottomless? coolfet? crossvolt ? densetrench? dome? ecospark? e 2 cmos tm ensigna tm fact? fact quiet series? smart start? star*power? stealth? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? trutranslation? uhc? ultrafet a a a star*power is used under license vcx?
|
